Search results for "Vector processor"
showing 5 items of 5 documents
Bit-Parallel Approximate Pattern Matching on the Xeon Phi Coprocessor
2014
Bit-parallel pattern matching encodes calculated values in bit arrays. This approach gains its efficiency by performing multiple updates within a machine word. An important parameter is therefore the machine word size (e.g. 32 or 64 bits). With the increasing length of vector registers, the efficient mapping of bit-parallel pattern matching algorithms onto modern high performance computing architectures is becoming increasingly important. In this paper, we investigate an efficient implementation of the Wu-Manber approximate pattern matching algorithm on the Intel Xeon Phi coprocessor. This architecture features a 512-bit long vector processing unit (VPU) as well as a large number of process…
Panel Discussion: Systems for Data Analysis What they AEE; what they Could be?
1985
CRANE: I’d like to pose a couple of questions: (1) Command Languages — A tool for the astronomer or for the programmer? (2) Portability — Holy Cow or Red Herring? I propose that we start with the first one and see how far we get. If we don’t get past that, fine. If we get on to the question of portability, this is also fine. Let me just open up the discussion by asking Rudi Albrecht to make a comment.
Image Processors for Digital Angiography Algorithms and Architectures
1986
After a period of experimental and clinical development,(1–9) digital processing of angiographic X-ray video image sequences is now routinely applied in clinical and research work. The clinical advantages offered by this approach have been discussed in several reports.(10–12) The primary application is the improved visualization of regions of the heart and circulation opacified by X-ray contrast material during angiographic and angiocardiographic examinations. More complex techniques are being developed for improved functional analysis based on digitized angiograms. Technically, the digital techniques also potentially offer improved means of acquiring, storing, and handling images when comp…
An optimized mass storage FFT for vector computers
1995
Abstract The performance of a segmented FFT algorithm which allows the out-of-core computation of the Fourier transform of a very large mass storage data array is presented. The code is particularly optimized for vector computers. Tests performed mainly on a CONVEX C210 vector computer showed that, for very long transforms, tuning of the main parameters involved leads to computation speed and global efficiency better than for FFTs performed in-core. The use of tunable parameters allows optimization of the algorithm on machines with different configurations.
SYSTOLIC GENERATION OF k-ARY TREES
1999
The only parallel generating algorithms for k-ary trees are those of Akl and Stojmenović in 1996 and of Vajnovszki and Phillips in 1997. In the first of them, trees are represented by an inversion table and the processor model is a linear aray multicomputer. In the second, trees are represented by bitstrings and the algorithm executes on a shared memory multiprocessor. In this paper we give a parallel generating algorithm for k-ary trees represented by generalized P–sequences for execution on a linear array multicomputer.